supports displayport (dp) specification version 1.3 and
embedded displayport (edp) specification version 1.4.
support 2 main link lanes at either 1.62gb/s or 2.7gb/s
link rate
supports input color depth 6, 8-bit per pixel in rgb
format
supports
enhanced framing mode
support vesa and cea timing standards up to 1920x1200
resolution in 8-bit input with 60hz refresh rate
support
dynamic refresh rate switching
fast and full link training for embedded displayport
system
support edp authentication: alternative scramble seed
reset and alternative framing
2 lane dp/edp bypass supported with high speed
buffer/switch integrated, pass through aux ch/hpd in edp / dp bypass
application
2 work modes: connect 27mhz crystal, inject 27mhz clock
de-ssc supported
high-speed mux integrated to support dp/edp output
pin-multiplexed with lvds output
programmable
lcd panel power sequence
support 18-bit single port, 18-bit dual port, 24-bit
single port and 24-bit dual port lvds output interface
support both openldi and spwg bit mapping for lvds
application
support panel select by gpio pins control or writing the
chip registers.
support flexible lvds output pin swapping for top or
bottom mount pcbs
support internal test pattern
blank panel
during invalid input
supports pwm backlight luminance level control through
aux channel, pwm pin and blup/bldn pin
support
dynamic backlight control
hot plug
detection
aux switch
integrated
loads boot rom automatically upon power up
serial boot rom data updated through i2c bus or aux
channel
support
power management mechanism through aux
offered in a 68-pin qfn package
描述
chrontel’s ch7513a is a low-cost, low-power semiconductor device that translates the embedded displayport signal to the lvds (low-voltage differential signaling). this innovative
displayport receiver with an integrated lvds transmitter is specially designed to target the all-in-one pc and the notebook market segments. through the ch7513a’s advanced decoding /encoding algorithm, the input dp/edp high-speed serialized video data can be seamlessly converted to lvds, a popular display technology for high-speed serial links in mid/large-sized lcd displays. leveraging the dp/edp’s unique source/sink “link training” routine, the ch7513a is capable of instantly bring up the video display to the lcd when the initialization process is completed between ch7513a and the graphic chip. the ch7513a is designed to meet the displayport (dp) specification version 1.3 and the embedded displayport specification version 1.4. in the device’s receiver block, which supports two dp/edp main link lanes input with data rate running at either 1.62gb/s or 2.7gb/s, can accept rgb digital formats in either 18-bit 6:6:6 or 24-bit 8:8:8 for lvds output up to 1920x1200. to comply with gpu’s new power saving scheme such as display frame rate reduction, the ch7513a is equipped with the dynamic refresh rate switching method, which can automatically reduce to the low refresh rate supported by the lvds panel. the integrated lvds transmitter supports the single port and the dual ports lvds outputs to drive display resolution up to wuxga (1920x1200). ch7513a supports panel select by gpio[0:3] pins control or writing the chip registers. to reduce emi emission, the ch7513a’s lvds encoder block has incorporated spread spectrum control and its spread percentage can be adjusted through the internal registers. the backlight on/off and the pwm are two luminance control functions designed in the ch7513a lvds power control module. the brightness control commands sent through aux channel can be dynamically translated by ch7513a and converted into lcd backlight control signal. the ch7513a will save the last setting of brightness level into the boot rom and restore it upon power up. the ch7513a can dynamically adjust backlight brigntness according to video stream to save power consumption and it supports osd display in this way. the ch7513a will immediately convert the dp/edp signal to lvds output after dp/edp link training is completed. this feature can be achieved by loading the panel’s edid and the ch7513a’s configuration settings in the serial boot rom connected to the ch7513a. during system power-up and upon completion of the dp/edp link training through aux channel, ch7513a will generate lvds signal according to the panel power-up timing sequencing stored in the boot rom.
