ch7105b-利来app官网

特征

• hdmi receiver compliant with hdmi 1.4 specifications


• support multiple output formats:
  
  
  • sdtv format (cvbs or s-video output, ntsc and pal)
  
  
  • analog rgb output for vga with triple 9-bit dac up to 200mhz pixel rate. sync signals can be provided in separated or composite manner. support vesa and cea timing standards up to uxga and 1920x1080@60hz
  
  
  
  
  
  
   
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• on-chip audio encoder which support 2 channel iis/s/pdif audio output


• vga output is compliant with vesa vsis v1r2 specification


• mcu embedded to handle the control logic


• support device boot up by automatically loading firmware from on-chip flash


• integrated edid buffer


• tv/vga connection detection supported


• hdmi input detection supported


• scaler engine integrated for 640x480 safe mode input supported in sdtv output application


• support auto power saving mode and low stand-by current


• support rgb to ycc conversion in itu-r bt.601 and 709 color space


• iic slave interface and hdmi ddc interface are available for debug and firmware update.


• low power architecture


• rohs compliant and halogen free package


• offered in 40-pin qfn package (5 x 5 mm)